Spread-spectrum clock (SSC) generation is used in the design of synchronous digital systems, especially those containing microprocessors, to reduce the spectral density of the electromagnetic interference (EMI) that these systems generate. A synchronous digital system is one that has an infinite spectral density. Practical synchronous digital systems radiate electromagnetic energy on a number of narrow bands spread on the clock frequency and its harmonics, resulting in a frequency spectrum that, at certain frequencies, can exceed the regulatory limits for electromagnetic interference.
To avoid this problem, spread-spectrum clocking is used. This consists of using one or a combination of a variety of spread spectrum techniques, such as modulating the clock frequency in a cyclic manner in order to reduce the peak radiated energy. The technique therefore reshapes the electromagnetic emissions of the system to comply with relevant electromagnetic compatibility (EMC) regulations.
Many modern computer servers use SSC to deliver data both over internal and external bus architectures, examples of such architectures being PCI (Peripheral Component Interconnect), PCI-X, and PCI Express. PCI Express is a bi-directional serial I/O interconnect standard that carries data in packets along two or more pairs of point-to-point data lanes, all of which constitute a link. Serial bit rates for PCI Express are 2.5 Gb/s or 5.0 Gb/s per lane direction.
One of the known difficulties with switches receiving data from multiple sources is that currently many such switches are incapable of processing traffic received by the switch from sources not having the same modulated SSC. Furthermore, even if data delivered to the switch emanates from different sources having the same modulated SSC, the switch itself would also need the same SSC signal to process the traffic effectively, reliably and accurately.
For example, in current PCI Express switch implementations, independent devices connected by a link operate within a clock domain, controlled by a crystal with a defined accuracy (eg +/−300 ppm, this being typical for current applications). The maximum frequency difference between any clock, i.e. the clocks of the one or more devices from where the data emanate, and the switch clock, is therefore 600 ppm. The difference in clock speeds between the device(s) and the switch therefore necessitates that the switch be provided with a means for accommodating or adjusting the clock rate of the received data, and to this effect, elastic buffers (e.g. first in, first out or FIFO buffers) exist at the receiving end of a link to counteract the clock frequency differences. The elastic buffer is configured to keep a read pointer (relating to amount of data received by the switch) and a write pointer (relating to an amount of data to be written to the buffer) within predetermined distances from each other so as to ensure that the buffer does not inadvertently at any point overflow (if the rate of reading data is lower than the rate of writing data for more than a certain time) or become empty (if the rate of writing data is lower than the rate of reading data for more than a certain time). Overflowing or running empty can cause data packets to become broken during passage through the switch, which leads to data corruption and generation of errors. The elastic buffer mechanism may, for example, add or discard predetermined redundant or junk data to balance the data rates across the link. The elastic buffer is large enough to accommodate the maximum frequency difference between the clocks, but this strategy unavoidably causes a small amount of latency to be added to the link.
In the case of SSC data delivery, although the data delivered may be identical, the frequency spectrum over which such is delivered can be much broader (for example a range of 5000 ppm modulated at a pulse-to-pulse frequency of 30 kHz), so instead of data being received at a particular clock frequency being ±300 ppm different to the clock frequency of the switch, the difference in the delivery rate of data from an SSC source can typically be anything up to ±300 ppm with an additional ±5000 ppm if both link partners have an independent SSC modulation This assumes a typical PCI Express application in which a clock signal is capable of being modulated in an SSC fashion so as to have a frequency of from +0% to −0.5% of a nominal unmodulated clock frequency of, say, 2.5 GHz. In other words, the SSC modulation is added to the ±300 ppm inaccuracy of the crystal generating the nominal signal clock, leading to a maximum relative clock frequency spread of ±5600 ppm. The provision of means whereby redundant data could be added or discarded from a bitstream to compensate for such differences is not only impractical in terms of link efficiency and elastic buffer FIFO size constraints, but would also impose an unacceptable degree of latency between the source of the data and its destination (i.e. a factor of 10 worse than the non-SSC scenario). The elastic buffer strategy cannot simply be scaled up to cope with SSC.